Keywords: شبکه بر چیپ (NoC); Multicore systems; Network-on-Chip (NoC); Wireless interconnections; Mesh-of-Tree (MoT); Communication protocol;
مقالات ISI شبکه بر چیپ (NoC) (ترجمه نشده)
مقالات زیر هنوز به فارسی ترجمه نشده اند.
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در صورتی که به ترجمه آماده هر یک از مقالات زیر نیاز داشته باشید، می توانید سفارش دهید تا مترجمان با تجربه این مجموعه در اسرع وقت آن را برای شما ترجمه نمایند.
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Adaptive routing algorithms; Congestion control management; Congestion information; Load balancing;
Keywords: شبکه بر چیپ (NoC); Congestion-aware core mapping; Network-on-Chip (NoC); Betweenness centrality;
Keywords: شبکه بر چیپ (NoC); Task-resource co-allocation; Network-on-Chip (NoC); Many-Core NoC; Heterogeneous; Computation and communication; Peak load; Energy hotspots; Cost budget; Linear programming (LP); Heuristic;
Keywords: شبکه بر چیپ (NoC); Hybrid cache hierarchy; Reconfigurable cache; Non-volatile memory (NVM); Three-dimensional integrated circuits; Dark-silicon; Chip-multiprocessor (CMP); Network-on-chip (NoC); Optimization;
Keywords: شبکه بر چیپ (NoC); Hardware Trojan; Hardware security; Network-on-chip (NoC); Bandwidth depletion; Deadlock; Livelock; Denial-of-service attack; Latency; Throughput;
Keywords: شبکه بر چیپ (NoC); Bio-inspired self-aware fault-tolerant routing protocol (BISFTRP); Particle Swarm Optimization (PSO); Network-on-chip (NoC); Intelligent adaptation; self-organization;
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Congestion control; Data flow control; Flit’s dropping; Quality-of-service (QoS) insurance
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); de Bruijn; Routing algorithm; Power consumption; Performance evaluation; Analytical model
Keywords: شبکه بر چیپ (NoC); Dynamic task mapping; Network-on-Chip (NoC); Multiprocessor System-on-Chip (MPSoC)
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Adaptive routing methods; Deadlock; Turn model; Hamiltonian path-based routing strategy
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Multi-processor system-on-chip (MPSoC); Router; Configurable core; Design methodology
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Bi-directional link; Double data rate
Energy and communication aware task mapping for MPSoCs
Keywords: شبکه بر چیپ (NoC); Task mapping; Core mapping; Energy and communication aware mapping; Multi-processor system-on-chip (MPSoC); Network-on-chip (NoC);
Models of computation for NoC mapping: Timing and energy saving awareness
Keywords: شبکه بر چیپ (NoC); Application modeling; Mapping; Network-on-Chip (NoC); Energy minimization; Performance analysis;
MCAR: Non-local adaptive Network-on-Chip routing with message propagation of congestion information
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Routing algorithm; Congestion awareness;
Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Field Programmable Gated Array (FPGA); NoC router; NoC synthesis;
Circuit design of Clos-based on-chip interconnection networks
Keywords: شبکه بر چیپ (NoC); Crossbars; Benes; Clos; Network-on-Chip (NoC); Schematic; Layout;
Energy-efficient contention-aware application mapping and scheduling on NoC-based MPSoCs
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Application mapping; Energy-efficient scheduling; Dynamic voltage scaling; Dynamic link frequency tuning
The design and implementation of a configurable MIMO detection system on the NOC-based multicore platform
Keywords: شبکه بر چیپ (NoC); MIMO detection; Multicore; Network-on-Chip (NOC); FPGA; Configurable; Large-scale MIMO;
A novel power efficient adaptive RED-based flow control mechanism for networks-on-chip
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Random Early Detection (RED) algorithm; Stochastic learning automata; Performance evaluation; Congestion control management; Power consumption
Transaction-based online debug for NoC-based multiprocessor SoCs
Keywords: شبکه بر چیپ (NoC); Transaction-based online debug; System-on-Chip (SoC); Network-on-Chip (NoC)
Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Interconnection network; Congestion-aware; Quality-of-Service (QoS)
MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Double Tail Sense Amplifier (DTSA); Dual edge triggered flip flop (DET); Clock gating with DTSA
A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip
Keywords: شبکه بر چیپ (NoC); Field-Programmable Gate Array (FPGA); Virtual Channel (VC); Network-on-Chip (NoC); Performance evaluation; Flit Data Width (FDW); Flit Buffer Depth (FBD)
From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Unified Modeling Language (UML); Fault tolerance; Application mapping; Multiprocessor System-on-Chip (MPSoC)
Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Application mapping; Evolutionary Algorithms; Genetic Algorithms; (Multi-objective) Optimization
Design and implementation of reconfigurable FIFOs for Voltage/Frequency Island-based Networks-on-Chip
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Voltage/Frequency Island (VFI); Globally Asynchronous Locally Synchronous (GALS); Reconfigurable FIFO
Avoiding request–request type message-dependent deadlocks in networks-on-chips
Keywords: شبکه بر چیپ (NoC); Streaming protocols; Network-on-chip (NoC); Message-dependent deadlock; Virtual channel
High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Power and performance; Topology synthesis optimization; Multiprocessor System-on-Chip (MPSoC)
Scalable load balancing congestion-aware Network-on-Chip router architecture
Keywords: شبکه بر چیپ (NoC); Interconnection network; Network-on-Chip (NoC); Congestion-aware; Load balance; Fault tolerance
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Mesh-of-Tree (MoT); Performance and cost evaluation; Virtual channel router
Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Network interface (NI); Coverage-driven functional verification; Intellectual property (IP) cores; Multi-processor system-on-chip (MPSoC)
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Keywords: شبکه بر چیپ (NoC); Network-on-Chip (NoC); Interconnection network; Power-efficient; Area-efficient; Congestion-aware
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Keywords: شبکه بر چیپ (NoC); Hardware–software co-design; Heterogeneous architectures; MPSoC design; Network-on-Chip (NoC); Mapping algorithms
Universal GALS Platform and Evaluation Methodology for Networks-on-Chip
Keywords: شبکه بر چیپ (NoC); network-on-chip (NoC); globally-asynchronous locally-synchronous (GALS); wormhole; evaluation methodology;
A variable frequency link for a power-aware network-on-chip (NoC)
Keywords: شبکه بر چیپ (NoC); 85.40.eInterconnection network; Network-on-chip (NoC); Dynamic frequency scaling; Power optimization; System-on-chip (SoC)
A high level power model for Network-on-Chip (NoC) router
Keywords: شبکه بر چیپ (NoC); Multi-processor System-on-Chip (MPSoC); Network-on-Chip (NoC); Interconnection network; Power model
Architectures and routing schemes for optical network-on-chips
Keywords: شبکه بر چیپ (NoC); Network-on-chip (NoC); Optical switch; Wavelength routed optical network (WRON); Recursive wavelength routed optical network (RCWRON)