Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Network-on-Chip (NoC) has emerged as a new paradigm to integrate large number of cores on a single silicon die. This paper presents a detailed study of Mesh-of-Tree (MoT) topology and explores its promise in communication infrastructure design for 2-D NoC. The performance and cost of MoT based NoC have been evaluated and compared with butterfly fat-tree (BFT) and two variants of mesh network for equal number of cores under same bisection width constraint. Simulation results under self-similar traffic show that MoT enjoys the advantage of having better performance than other topologies, whereas, it consumes lesser average packet energy than the mesh network that connects single core to each router. In the area front, MoT occupies almost similar area like mesh network connects single core to each router. The MoT network has also been evaluated under a set of real benchmark applications and compared with the above mentioned topologies. Simulation results under application specific traffic also show the competitive potential of MoT topology in NoC design. Moreover, due to lesser connectivity of the routers, synthesis result shows that MoT network can be operated at higher frequency than others. Taking all these facts into consideration, this paper establishes that like mesh and BFT, MoT can also be applied in designing NoC based systems. This paper also focuses on the limitations of MoT and other tree based topologies in NoC design in current technology and enumerates probable solutions to make them more acceptable.