کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
540136 | 871288 | 2009 | 7 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: A variable frequency link for a power-aware network-on-chip (NoC) A variable frequency link for a power-aware network-on-chip (NoC)](/preview/png/540136.png)
Although the technology scaling has enabled designers to integrate a large number of processors onto a single chip realizing chip multi-processor (CMP), problems arising from technology scaling have made power reduction an important design issue. Since interconnection networks dissipate a significant portion of the total system power budget, it is desirable to consider interconnection network's power efficiency when designing CMP. In this paper, we present a variable frequency link for a power-aware interconnection network using the clock boosting mechanism, and apply a dynamic frequency scaling (DFS) policy, that judiciously adjusts link frequency based on link utilization parameter. Experimental result shows that history-based DFS successfully adjusts link frequency to track actual link utilization over time, demonstrating the feasibility of the proposed link as a power-aware interconnection network for system-on-chip (SoC).
Journal: Integration, the VLSI Journal - Volume 42, Issue 4, September 2009, Pages 479–485