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• A new LUT scheme that utilizes memristors as NV storage elements while not using nanocrossbar structure.
• LUT scheme does not incur in sneak path current generation.
• Permits simultaneous WRITE operation to all memristors connected to a BL; hence WRITE time decreases considerably.
• READ delay is significantly less than previous schemes. Hence suitable for FPGA.
• No write half-select problem and hence, it requires a smaller number of power rails for its operation.
This paper presents a scheme for designing a memristor-based look-up table (LUT) in which the memristors are connected in rows and columns. As the columns are isolated, the states of the unselected memristors in the proposed scheme are not affected by the WRITE/READ operations; therefore, the prevalent problems associated with nanocrossbars (such as the write half-select and the sneak path currents) are not encountered. Extensive simulation results of the proposed scheme are presented with respect to the WRITE and READ operations; its performance is compared with previous LUT schemes using memristors as well as SRAMs. It is shown that the proposed scheme is significantly better in terms of WRITE time and energy dissipation for both memory operations (i.e. WRITE and READ); moreover it is shown that the READ delay is nearly independent of the LUT dimension. Simulation using benchmark circuits for FPGA implementation show that the proposed LUT offers significant improvements also at this level.
Journal: Integration, the VLSI Journal - Volume 55, September 2016, Pages 1–11