کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
865499 | 909671 | 2009 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Universal GALS Platform and Evaluation Methodology for Networks-on-Chip
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی (عمومی)
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چکیده انگلیسی
A networks-on-chip (NoC) cost-effective design method was given based on the globally-asynchronous locally-synchronous (GALS) interconnect structure. In this method, the synchronous mode was used to transmit data among routers, network interface (NI), and intellectual property (IP) via a synchronous circuit. Compared with traditional methods of implementing GALS, this method greatly reduces the transmission latency and is compatible with existing very large scale integration (VLSI) design tools. The platform designed based on the method can support two kinds of packetizing mechanisms, any topology, several kinds of traffic, and many configurable parameters such as the number of virtual channels, thus the platform is universal. An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Tsinghua Science & Technology - Volume 14, Issue 2, April 2009, Pages 176-182
Journal: Tsinghua Science & Technology - Volume 14, Issue 2, April 2009, Pages 176-182
نویسندگان
Lin (æä¸ä¿), Su (è å), Jin (éå¾·é¹), Zeng (æ¾çå
),