Low space-complexity and low power semi-systolic multiplier architectures over GF(2m) based on irreducible trinomial

• Propose low power bit-serial and digit-serial semi-systolic multiplier architectures over GF(2m).
• Develop a new Progressive Reduction Technique (PPR).
• Develop affine and nonlinear task scheduling functions.
• Develop affine and nonlinear task projection onto processors.
• Provide ASIC Implementation for proposed and previously published designs.

This paper proposes a three bit-serial and digit-serial semi-systolic GF(2m) multipliers using Progressive Product Reduction (PPR) technique. These architectures are obtained by converting the GF(2m) multiplication algorithm into an iterative algorithm using systematic techniques for scheduling the computational tasks and mapping them to Processing Elements (PE). Three different semi systolic arrays were obtained. ASIC implementation of the proposed designs and previously published schemes were used to verify the performance of the proposed designs. One proposed design has at least 29% lower area compared to previously published bit/digit serial multipliers. This design has also at least 70% lower power compared to previously published bit/digit serial multipliers. Another proposed design has at least 12% lower power-delay product (PDP) compared to previously published bit/digit serial multipliers. This makes the proposed designs more suited to resource-constrained embedded applications.