Static statistical MPSoC power optimization by variation-aware task and communication scheduling

Corner-case analysis is a well-known technique to cope with occasional deviations occurring during the manufacturing process of semiconductors. However, the increasing amount of process variation in nanometer technologies has made it inevitable to move toward statistical analysis methods, instead of deterministic worst-case-based techniques, at all design levels. We show that by statically considering statistical effects of random and systematic process variation on performance and power consumption of a Multiprocessor System-on-Chip (MPSoC), significant power improvement can be achieved by static software-level optimizations such as task and communication scheduling. Moreover, we analyze and show how the changes in the amount of process variability as well as values of other system constraints affect the achieved power improvement in such system-level optimizations. We employ a mixed-level model of MPSoC critical components so as to obtain the statistical distribution of frequency and power consumption of MPSoCs in presence of both within-die and die-to-die process variations. Using this model, we show that our proposed statistical task scheduling algorithm can achieve substantial power reduction under different values of system constraints. Furthermore, the effectiveness of our proposed statistical task scheduling approach will even increase with the increasing amount of process variation expected to occur in future technologies.