کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
462875 | 696920 | 2011 | 12 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: 3D floorplanning of low-power and area-efficient Network-on-Chip architecture 3D floorplanning of low-power and area-efficient Network-on-Chip architecture](/preview/png/462875.png)
Network-on-Chip (NoC) architectures have been adopted by chip multi-processors (CMPs) as a flexible solution to the increasing delay in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. In this paper, we propose three 3D floorplanning methods for a Triplet-based Hierarchical Interconnection Network (THIN) which is a new high performance NoC. The proposed floorplanning methods use both Manhattan and Y-architecture routing architectures so as to improve the performance, reduce the power consumption and area requirement of THIN. A cycle accurate simulator was developed based on Noxim NoC simulator and ORION 2.0 energy model. The proposed floorplanning methods show up to 24.69% energy and 8.84% area reduction at best compared with 3D Mesh. Our analysis concludes that THIN is not only a feasible but also a low-power and area-efficient NoC at physical level.
Journal: Microprocessors and Microsystems - Volume 35, Issue 5, July 2011, Pages 484–495