Fault tolerant routing algorithm based on the artificial potential field model in Network-on-Chip

Recent advances in semiconductor technology enable the VLSI chips to integrate hundreds of intellectual properties with complex functionality. However, as the chip scales, the probability of faults is increasing, making fault tolerance a key concern in designing the large scale chips. The fault tolerant routing algorithms can guarantee sustained communication even the faults exist. It is an efficient technique to achieve fault tolerance in Networks-on-Chip. In this paper, we propose a new model based on the theory of artificial potential field (APF) to design various fault tolerant routing algorithms. In our model, the faults are considered as the poles of the repulsive potential fields while the destinations as the poles of the attractive potential fields. Messages are attracted to destinations and repelled by faults in the combined artificial potential field. The parameters used in the proposed APF based model are optimized through theoretical analysis and simulation experiments. They can support flexible fault tolerant routing algorithms. Finally, we evaluate the performance of the proposed fault tolerant routing algorithm based on the APF model in 2D-mesh NoCs with random faults. The simulation results show that the proposed APF based model is feasible and the routing algorithm can maintain good network performance.