Variation and defect tolerance for diode-based nano crossbars

Bottom-up self-assembly nanofabrication process yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled nanodevices. Therefore, it is one of the major design challenges to tolerate variation and defects in emerging nano architectures. In this paper, we present different solutions for variation tolerant logic mapping for molecular (diode-based) crossbar array nano architectures using Simulated Annealing as well as a heuristic algorithm. Experimental results and comparisons with exhaustive search and defect-unaware mapping shows the effectiveness of the proposed methods in variation and defect tolerance as well as run time improvement.