A new low power reconfigurable decimation–interpolation and masking based filter architecture for channel adaptation in cognitive radio handsets

Cognitive radio (CR) aims at exploiting the scarce radio spectrum in a smart flexible way to provide opportunistic spectrum access to secondary users for whom the frequency bands have not been licensed. The key tasks in a CR are to sense the spectral environment over a wide frequency band and allow unlicensed secondary users (CR users) to dynamically transmit/receive data over frequency bands unutilized by licensed primary users. Thus the CR transceiver should dynamically adapt its channel (frequency band) in response to the time-varying frequencies of wideband signal for seamless communication. In this paper, an architecture for implementing a low power reconfigurable channel filter based on decimation, interpolation and frequency masking techniques for dynamic channel adaptation in a CR terminal is presented. The proposed architecture is unique in a way that it is capable of extracting channels with varying bandwidths corresponding to the channel spacing of different time-varying frequencies of wideband signal. Design examples show that proposed architecture offers 90% complexity reduction over conventional Per-Channel approach. The implementation on Xilinx Virtex 2v3000ff1152-4 FPGA results in an average gate count reduction of 10.7% and has a power reduction of 5.9% over the Per-Channel approach. The proposed architecture offers 95.7% area-time complexity reduction when compared to the reconfigurable FIR filter.