An Efficient VLSI Architecture for Matrix Based RNS Backward Converter

Residue Number System (RNS) is the important research area from last five decades. Forward & backward conversion process is the bottle neck which limits the use of RNS for computing needs. In this paper, we proposed an efficient VLSI architecture for Matrix based RNS backward converter. We analysed the performance of proposed architecture for different modulo sets of size up to ten . Implemented using TSMC standard cell 180 nm CMOS technology libraries and result analysis indicated that, the performance of proposed converter achieved about 59% area reduction and 30% efficient with respective to Time-Delay Product when compared to the state of art Backward converters.