Keywords: ریاضی کامپیوتر; Logic design; Redundant binary; Adder; Computer arithmetic;
مقالات ISI ریاضی کامپیوتر (ترجمه نشده)
مقالات زیر هنوز به فارسی ترجمه نشده اند.
در صورتی که به ترجمه آماده هر یک از مقالات زیر نیاز داشته باشید، می توانید سفارش دهید تا مترجمان با تجربه این مجموعه در اسرع وقت آن را برای شما ترجمه نمایند.
در صورتی که به ترجمه آماده هر یک از مقالات زیر نیاز داشته باشید، می توانید سفارش دهید تا مترجمان با تجربه این مجموعه در اسرع وقت آن را برای شما ترجمه نمایند.
Keywords: ریاضی کامپیوتر; Approximate computing; Numeric function approximation; Two-variable; Least-squares; Computer arithmetic;
Keywords: ریاضی کامپیوتر; Computer arithmetic; Decimal arithmetic; Coarse-grain architecture; Reconfigurable hardware;
Keywords: ریاضی کامپیوتر; Computer arithmetic; Floating-point square root; Modified non-restoring algorithm; Reversible controlled-subtract-multiplex; Optimized reversible controlled-subtract-multiplex;
Keywords: ریاضی کامپیوتر; Computer arithmetic; Binary coded decimal (BCD) encoding; Binary and BCD multiplication; Binary to BCD conversion
Keywords: ریاضی کامپیوتر; Computer arithmetic; Computational methods; Exact computation; Rational processing; Mathematical model; Computational efficiency
A 1-V to 0.29-V sub-100-pJ/operation ultra-low power fast-convergence CORDIC processor in 0.18-μm CMOS
Keywords: ریاضی کامپیوتر; Angle recoding; CORDIC; Computer arithmetic; Ultra-low power design; Ultra-low voltage operation; Sub/near-threshold operation; VLSI design;
(5â
+â
2âlogâ
nâ)ÎG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling
Keywords: ریاضی کامپیوتر; Diminished-1 encoding; Modulo-(2n + 1) subtraction; Modulo-(2n + 1) addition; Unified adder/subtractor; Residue number system; Computer arithmetic;
A new area-efficient BCD-digit multiplier
Keywords: ریاضی کامپیوتر; BCD enconding; Computer arithmetic; FPGA; IoT; Multiplier;
An Efficient VLSI Architecture for Matrix Based RNS Backward Converter
Keywords: ریاضی کامپیوتر; Residue Number System; Chinese remainder theorem(CRT); Backward Convertor; Computer Arithmetic
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers
Keywords: ریاضی کامپیوتر; Decimation filter; Signal processing; Computer arithmetic; Carry-Save number
FPGA realization of multi-scroll chaotic oscillators
Keywords: ریاضی کامپیوتر; FPGA; Chaos; Multi-scroll; Computer arithmetic; VHDL; Maximum Lyapunov exponent; Chua’s circuit; Saturated function series
Truncated squarer with minimum mean-square error
Keywords: ریاضی کامپیوتر; Squarer; Truncated multiplier; Computer arithmetic; VLSI systems
An approximate logarithmic squaring circuit with error compensation for DSP applications
Keywords: ریاضی کامپیوتر; Approximate squaring; Arithmetic circuits; Computer arithmetic; Logarithm approximation; Logic synthesis; Digital signal processing
Applicability of approximate multipliers in hardware neural networks
Keywords: ریاضی کامپیوتر; Hardware neural network; Iterative logarithmic multiplier; FPGA; Digital design; Computer arithmetic
Fast parallel prefix logic circuits for n2n round-robin arbitration
Keywords: ریاضی کامپیوتر; Circuits for networking; Computer arithmetic; Logic synthesis; Priority encoder; Timing optimization
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Keywords: ریاضی کامپیوتر; Computer arithmetic; Elementary function evaluation; Linear approximation; Non-uniform segmentation; FPGA
A study of decimal left shifters for binary numbers
Keywords: ریاضی کامپیوتر; Decimal arithmetic; Computer arithmetic; Decimal shifter; Barrel shifter; Hardware designs; Binary integer decimal
An iterative logarithmic multiplier
Keywords: ریاضی کامپیوتر; Computer arithmetic; Digital signal processing; Multiplier; Logarithmic number system; FPGA
Efficient modulo 2n±1 squarers
Keywords: ریاضی کامپیوتر; Squarers; Modulo arithmetic; Residue number system; Computer arithmetic; Booth encoding
Optimized design of parallel carry-select adders
Keywords: ریاضی کامپیوتر; Adders; Carry Select; Design; VLSI; Computer arithmetic
Multiplication in GF(2m): area and time dependency/efficiency/complexity analysis.
Keywords: ریاضی کامپیوتر; ECC; finite fields arithmetic; GF(2m); computer arithmetic; Karatsuba-Ofman
Formal proof of prefix adders
Keywords: ریاضی کامپیوتر; Prefix adders; Computer arithmetic; Semi-group; VLSI
An improved maximally redundant signed digit adder
Keywords: ریاضی کامپیوتر; Computer arithmetic; Maximally redundant signed-digit number system; Signed digit adder; Weighted bit-set encoding; Inverted encoding of negabits; Logical techniques and design
An efficient architecture for designing reverse converters based on a general three-moduli set
Keywords: ریاضی کامپیوتر; Reverse converter; Residue to binary converter; Residue number system (RNS); Computer arithmetic; New chinese remainder theorem 1 (New CRT-I)
A new high dynamic range moduli set with efficient reverse converter
Keywords: ریاضی کامپیوتر; Residue number system; Computer arithmetic; Residue to binary converter; Chinese remainder theorem (CRT); RNSResidue number system (RNS); Computer arithmetic; Residue to binary converter; Chinese remainder theorem (CRT)
Versatile multiplier architectures in GF(2k)GF(2k) fields using the Montgomery multiplication algorithm
Keywords: ریاضی کامپیوتر; Computations in finite fields; Computer arithmetic; Montgomery multiplication; Pipeline; Versatile design; VLSI
Integer squarers with overflow detection
Keywords: ریاضی کامپیوتر; Computer arithmetic; Integer squarers; Overflow detection
Dual-mode floating-point adder architectures
Keywords: ریاضی کامپیوتر; Quadruple precision; Double precision; Single precision; Adder; Floating-point; Computer arithmetic; Dual-mode; Hardware designs
Enhanced-functionality multipliers
Keywords: ریاضی کامپیوتر; Computer arithmetic; Integer multipliers; Truncated multipliers; Low-power
Partial product reduction by using look-up tables for M×N multiplier
Keywords: ریاضی کامپیوتر; Computer arithmetic; Arithmetic and logic structures; High speed arithmetic; Multiplication
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Keywords: ریاضی کامپیوتر; Arithmetic unit; Carry-free addition; Computer arithmetic; redundant number representation; Signed-digit number system
Design and characterization of NULL convention arithmetic logic units
Keywords: ریاضی کامپیوتر; Asynchronous logic design; Delay-insensitive circuits; Self-timed circuits; Computer arithmetic; Arithmetic logic unit
The delay of circuits whose inputs have specified arrival times
Keywords: ریاضی کامپیوتر; Circuit; Straight-line program; Depth; Size; Prefix problem; Computer arithmetic; VLSI design; Static timing analysis
A novel IEEE rounding algorithm for high-speed floating-point multipliers
Keywords: ریاضی کامپیوتر; Computer arithmetic; Combinational circuits; Floating-point multiplication; Rounding
Delay optimization of linear depth boolean circuits with prescribed input arrival times
Keywords: ریاضی کامپیوتر; Circuit; Straight-line program; Depth; Delay; Computer arithmetic; VLSI design
Dual-mode floating-point multiplier architectures with parallel operations
Keywords: ریاضی کامپیوتر; Quadruple precision; Double precision; Single precision; Multiplier; Floating-point; Computer arithmetic; Rounding; Normalization
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Keywords: ریاضی کامپیوتر; NULL convention logic; Gate-level pipelining; NULL cycle reduction; Computer arithmetic;