Truncated squarer with minimum mean-square error

• A binary squarer with reduced area and power dissipation.
• Improved accuracy with respect to other truncated squarer.
• Easy hardware design.
• 90 nm CMOS implementation data provided.

Squaring is an important arithmetic operation required in a multitude of applications. In this paper we present a truncated squarer that, with an n-bit input, produces its output on a number of bits that can be defined at design time in the [n,2n] range. For each configuration, some of the partial products are unformed, to reduce area and power, and error compensation function is introduced to minimize the mean-square error. As shown by synthesis results in 90 nm CMOS, the proposed squarer has similar hardware complexity as previously proposed architectures but provides lower approximation error.The implementation of the proposed circuit can be automated with the aid of a provided Matlab script.