Analysis and optimization of the two-stage pipelined SAR ADCs

The two-stage pipelined SAR ADC (Successive Approximation Register Analog-to-Digital Convertor) is analyzed which consists of a SAR-based MDAC and a SAR ADC, with 1 bit redundancy to relax the requirement for the sub-ADC decision in accuracy. The stage resolution determines the performance of the ADC, which is optimized for high performance in linearity, noise, power, and speed. For the resolution of 10-bit, the optimal per stage resolution is about 5-bit in the first stage and 6-bit in the second stage. According to the analysis, a 10-bit two-stage pipelined SAR ADC was designed and fabricated in 180 nm CMOS, which achieves 56.04 dB SNDR and 5 mW power consumption from 1.8 V power supply at 50 MS/s.