Development of a simulator for analyzing some performance parameters of nanoscale strained silicon MOSFET-based CMOS inverters

Owing to the persisting technological importance of Strained-Si (S–Si) metal-oxide-semiconductor field-effect transistors (MOSFETs) and the hurdles offered by source (S) and drain (D) series resistances in the nanometer regime, a simulator has been developed for evaluating the voltage transfer characteristics (VTC) and analyzing some performance parameters of such devices-based CMOS inverters. The algorithms used for framing the simulator are based on analytical equations which can accurately estimate the noise margin (NM), dynamic current, and so on. The effects of strain on the circuit performance have also been investigated, with emphasis on the variations of drain current dependent transconductance ratio. A scope of using high-k dielectric materials along with strain is also explored. The algorithms proposed in this work are not only restricted to strained-Si MOSFETs but can also be applied to any novel device structure and complex digital logics, presented as case studies.