Thermal-aware floorplanner for 3D IC, including TSVs, liquid microchannels and thermal domains optimization

• We have designed an effective algorithm to optimize the placement of functional units and through silicon vias.
• We have also integrated an approximated (but accurate) thermal model inside the optimization loop.
• We have added an optimizer for active cooling (liquid channels).
• We propose a novel technique based on air channel placement designed to isolate thermal domains.

3D stacked technology has emerged as an effective mechanism to overcome physical limits and communication delays found in 2D integration. However, 3D technology also presents several drawbacks that prevent its smooth application. Two of the major concerns are heat reduction and power density distribution. In our work, we propose a novel 3D thermal-aware floorplanner that includes: (1) an effective thermal-aware process with three different evolutionary algorithms that aim to solve the soft computing problem of optimizing the placement of functional units and through silicon vias, as well as the smooth inclusion of active cooling systems and new design strategies, (2) an approximated thermal model inside the optimization loop, (3) an optimizer for active cooling (liquid channels), and (4) a novel technique based on air channel placement designed to isolate thermal domains have been also proposed. The experimental work is conducted for a realistic many-core single-chip architecture based on the Niagara design. Results show promising improvements of the thermal and reliability metrics, and also show optimal scaling capabilities to target future-trend many-core systems.

We have designed an integrated framework based on a set of algorithms to place functional units, air channels, through silicon vias and liquid channels. Our framework performs an incremental floorplan design to optimize both performance and maximum temperature in the 3D-IC. Figure optionsDownload as PowerPoint slide