Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM

In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.