Keywords: Loadless; Near-threshold; Low-power; SRAM; Memory-cell;
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Keywords: Nanoprobing; Probing; NBTI; PBTI; BTI; In-situ characterization; Induced aging; Transistor aging; Transistor degradation; SRAM; AFM; HCI; TDDB; RTN; Operating lifetime; Localized variation; Intra-die comparison; Inter-die comparison;
Keywords: Simulation; Single-event effect; SRAM; Single-event upset; SOI; Experiment; Neutron;
Keywords: Memory; Charge trapping; WORM; SRAM;
Keywords: Organic electronics; Thin film transistors; Inverters; SRAM
Keywords: Communication; Health and safety; Site remediation; Stakeholders; Sustainability assessment; Sustainable remediation; Social indicators; ABC; Assessment, Benefits and Costs; BATNEEC; Best Available Techniques Not Entailing Excessive Costs; CBA; Cost-Benef
Keywords: Scratch pad memory; SRAM; Process variations; Dynamic voltage and frequency scaling
Keywords: Polyimide; Electrical memory; SRAM;
Keywords: Polynaphthalimide; Triphenylamine; Fluorene; SRAM; WORM
Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM
Keywords: RC delay; Nanoplate; Vertical FET; Channel pitch; SRAM; Read static noise margin; Process variation;
Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability
Keywords: Planar; SoC; FinFET; BTI; SRAM; SNM; Vmin;
Analysis of 6â¯T SRAM cell in sub-45â¯nm CMOS and FinFET technologies
Keywords: SRAM; Nanotechnology; Process variability; Aging effects; Radiation effects;
Static noise margin trade-offs for 6T-SRAM cell sizing in 28â¯nm UTBB FD-SOI CMOS technology
Keywords: CMOS memory circuits; Low voltage; Process variation; SRAM; Static noise margin; Sub-threshold operation; Yield;
Investigation of BTI characteristics and its behavior on 10Â nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack
Keywords: FinFET; Bias temperature instability (BTI); Vt variability; Ring oscillator; SRAM; Static noise margin (SNM); Write margin (WRM);
Technical, financial, economic and environmental pre-feasibility study of geothermal power plants by RETScreen - Ecuador's case study
Keywords: FAM; Financial Analysis model; SRAM; Sensitivity and Risk Analysis Models; NPV; Net Present Value; PUGR-E; Plan for the Utilization of Geothermal Resources in Ecuador; UNFCCC; United Nations Framework Convention on Climate Change; IGA; International Geoth
Bias temperature instability in scaled CMOS technologies: A circuit perspective
Keywords: High-k dielectrics; Metal gate; BTI; RTN; SRAM; Ring-oscillators; CMOS;
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology
Keywords: Sense amplifier; FinFET; Offset tolerance; SRAM;
Robust TFET SRAM cell for ultra-low power IoT applications
Keywords: SRAM; Tunnel FET; Ultra-low power; IoT; Half-select issue;
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design
Keywords: SRAM; LUT; FPGA; Leakage power; Static noise margin (SNM);
A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations
Keywords: FinFET; SRAM; CMOS; Sub-threshold; Write Margin;
A novel charge recycle read write assist technique for energy efficient and fast 20â¯nm 8T-SRAM array
Keywords: SRAM; Assist technique; Charge recycling; Half-selected cell; Leakage current;
Impact of line edge roughness on the performance of 14-nm FinFET: Device-circuit Co-design
Keywords: FinFET; Line edge roughness; Resist-defined; Spacer-defined; SRAM; Variability;
Multi-Poisson process analysis of real-time soft-error rate measurements in bulk 65Â nm and 40Â nm SRAMs
Keywords: Soft error rate; Real-time measurements; Poisson process; SRAM; Atmospheric neutrons; Alpha-particle emitters;
Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations
Keywords: SRAM; Time dependent dielectric breakdown (TDDB); Monte Carlo simulation; Reliability; Performance; Configuration;
A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor
Keywords: SRAM; Short circuit current; Stability; Differential read; Process variation;
Low energy proton induced single event upset in 65Â nm DDR and QDR commercial SRAMs
Keywords: SRAM; Low energy proton; Single event upset; Direct ionization;
Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor
Keywords: High-k; SRAM; Junctionless transistor; Dual metal gate engineering; TCAD;
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources
Keywords: Soft errors; Single event effects; Single Event Upset; Radiation effects; SRAM; Neutrons;
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS
Keywords: SRAM; Cross-point; Data-aware; Read-half-select; Sub-threshold; Ultra-low power;
Efficient defect identification of soft failures induced by device local mismatch for nano-scale SRAM yield improvement
Keywords: Device; Local mismatch; Fault isolation; Nano-probing; Test; SRAM;
Design and investigation of variability aware sense amplifier for low power, high speed SRAM
Keywords: Current latch sense amplifier; Offset; SRAM; Inter die variations; Intra die variations;
Silicon nanotube SRAM and its SEU reliability
Keywords: Heavy ions; SiNT FET; Single event upset; Static noise margin; SRAM; TCAD;
Highly flexible SRAM cells based on novel tri-independent-gate FinFET
Keywords: Tri-independent-gate; FinFET; SRAM; Read stability and speed;
Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM
Keywords: Carbon nanotube field effect transistor; Electrostatic doped; Dynamic configuration; Static noise margin; Low power; SRAM;
Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design
Keywords: FinFET; Line edge roughness; Resist defined; Spacer defined; SRAM; Work function variation;
Memory write speed up via multi voltage driver on CeidMem Library
Keywords: SRAM; Static random access memory; Cache; Multi voltage; VLSI; Standard cell library;
Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product
Keywords: Defect; Gate oxide; HTOL; Reliability; Testing; SRAM
Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies
Keywords: High-k dielectrics; Metal gate; BTI; TDDB; RTN; SRAM; Ring-oscillators; CMOS;
Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs
Keywords: SRAM; SBD; NBTI; PBTI; RSNM modeling; FinFET;
Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs
Keywords: JAM; Dual-k spacer; SRAM; SCEs;
Charge recycling 8T SRAM design for low voltage robust operation
Keywords: SRAM; Bit-line charge recycling; Low power
Power efficient SRAM design with integrated bit line charge pump
Keywords: SRAM; Low power; Charge pump; Bit line;
URFA-Update based register file architecture with partial register write for energy efficiency
Keywords: Low-power design; Register file; Microprocessors; SRAM;
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process–voltage–temperature variations
Keywords: Boost-less; FinFET; Process–voltage–temperature; SRAM; Sub-threshold; Ultra-low power
Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability
Keywords: Nanowire transistor; Low voltage operation; SRAM; Static noise margin; Variability
Impact of dynamic voltage scaling and thermal factors on SRAM reliability
Keywords: SRAM; Critical charge; Supply voltage; Critical charge profile; Dynamic voltage scaling; Semi-dynamic method; Soft error; Dependent critical charge curve;
Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies
Keywords: Circuit reliability; SRAM; Single event upsets; Soft error rate; Dynamic data stability; 8T cells;
SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS
Keywords: CMOS memory circuits; SRAM; Energy minimization; Multi-Vth; Leakage reduction; Power reduction
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET
Keywords: Symmetric DGMOS; Lateral straggle; Variable gain amplifier; Amplitude Modulator; Modulation index; Efficiency; SRAM; Static Noise Margin
Sub-threshold 10T SRAM bit cell with read/write XY selection
Keywords: Sub threshold Design; SRAM; Leakage; Half selected bit cells; Bit cell; XY selection