A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process–voltage–temperature variations

A novel 20 nm FinFET based 7T SRAM cell is presented. Proposed 7T SRAM cell involves the breaking-up of feedback between the true storing nodes which enhances the write-ability of the cell at ultra-low voltage power supply without boosted supply and write assist. The read decoupling and feedback cutting makes proposed 7T SRAM cell more robust to process variations in sub-threshold regime. For proposed 7T SRAM cell, the mean and standard-deviation (μ/σ) ratio of hold static noise margin is 31.5% higher than that of conventional iso-area 5T SRAM cell at 0.5 V VDD. The 7T SRAM cell has 66.4% higher μ/σ of read margin as that of 5T SRAM cell at 0.25 V VDD. The write static noise margin of 7T SRAM cell is ~50% of VDD for all VDD values whereas 5T SRAM cell fails to write. During write ‘0’, the proposed cell consumes only 0.11× power as that of 5T SRAM cell at 0.8 V VDD. The read operation of 7T SRAM cell consumes 0.34× lesser power than 5T SRAM cell read operation for all values of bit-line capacitances at 0.2 V VDD. At 0.2 V VDD, the 7T SRAM cell has 0.46× lower write ‘0’ delay as that of 5T SRAM cell. The write delay of 7T SRAM cell is 0.32× lower as that of 5T SRAM cell at 0.8 V VDD. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low voltage supply without any write assist in 20 nm FinFET technology node.