A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistors is proposed here which increases cell stability along with maintaining the most desirable differential read technique for faster read. The read SNM of the proposed cell is 154%, 31% and 58% large than that of the conventional 6T-SRAM cell and 2 other 7T-SRAM cells [5,6] compared here. Various factors such as short circuit current reduction, use of single write access transistor, partial bit line swing etc. reduces the overall energy consumption of the proposed cell by 41% compared to 6T-SRAM cell. The proposed cell is also compared with an eight transistor based read disturbance free SRAM cell. The cell delay of the proposed cell is around 55% lesser than that of the 8T-SRAM cell. Besides CMOS the performance achievement of the proposed 7T-SRAM cell is also validated at miniaturized dimension of 20 nm using FinFET based predictive technology model library.