Design and investigation of variability aware sense amplifier for low power, high speed SRAM

Reducing the input referred offset voltage of a sense amplifier (SA) provides remarkable returns in terms of reliability and energy conservation in static random access memory (SRAMs), which consume dominating portion of total power in modern ICs. High-reliability-applications benefit significantly from a low offset SA which can operate at high speed. However, low offset SAs tend to have significant overheads in terms of area, speed and complexity. In this paper we introduce a high speed SA that employs a self correction scheme to greatly minimize its input referred offset. Minimal calibrating circuitry limits the area and energy overheads. Sensing and failure mechanisms have been described for the first time in terms of resistance states of critical paths in SA, to provide a new and more basic dimension in the analysis of the offset problem. We implemented a CMOS logic- compatible, 4 Kb SRAM macro, in commercial UMC 65 nm, using the proposed SA namely, self correcting sense amplifier (SCSA). Performance analysis reveals a 60% reduction in standard deviation of input referred offset in SCSA compared to conventional current latch sense amplifier (CLSA). Compared to another modern low offset alternative, SCSA have a 78% lower sensing delay and 19% lower active power consumption resulting in 82% reduction in the power delay product.