Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

• Impacts of S-factor and Vth variability on SNM and Vddmin were demonstrated.
• SPICE model parameters of NW Tr. were extracted from measurement data.
• Ideal subthreshold slope characteristic was a key to obtain the large SNM.
• Voltage scaling of SRAM composed of NW Tr. was not limited by Vth variations.

An ultra-low voltage performance of nanowire-transistors-based SRAM cell is investigated using the SPICE model parameters extracted from measurement data. The impact of S-factor and threshold voltage variations on the static noise margin and the minimum operating voltage is evaluated in nanowire transistor as well as in planar bulk transistor and quasi-planar bulk transistor. The performance benefits of undoped nanowire-transistor-based SRAM are measured in terms of the read stability for low voltage and low off leakage current operation.