Trigger voltage walk-out phenomenon in SOI lateral insulated gate bipolar transistor under repetitive electrostatic discharge stresses

Trigger voltage walk-out phenomenon is found in SOI LIGBT’s under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.