Sub-threshold 10T SRAM bit cell with read/write XY selection

• We detail the implementation of two options of 10T SRAM bit cells for ULV operation in 28 nm CMOS bulk.
• We give a comparative study of SRAM bit cells for ULV operation based on standard metrics.
• We demonstrate improvements with respect to leakage current, read failures, read port parasitic consumption.
• We validate experimentally the circuit proposals in 28 nm CMOS bulk.
• We confront results about standard SRAM metrics to the ones of most representative bit cells in literature.

New SRAM bit cell architectures have been proposed recently as solutions to the limitations of the six-transistor (6T) SRAM bit cell in term of minimum supply voltage, VDDMIN. There is no demonstrated bit cell as superior under ultra-low supply voltage like the 6T bit cell at nominal voltage. Main limitations concern first the ratio between the read current and the standby current at the lowest operating voltage, second the bit cell robustness to perturbations and third the data sensing sensitivity, among other but minor limitations. The paper presents two proposals of ten-transistor (10T) Ultra-Low-Voltage bit cell for 0.3 V operation and processed in 28 nm LP CMOS bulk. Simulation results are compared to experimental results to demonstrate a satisfying operation at Ultra-Low supply voltage.