Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability

In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation.