کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6945867 | 1450520 | 2018 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20Â nm System on Chip (SoC), 16Â nm FinFET (16FF) and 10Â nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 81, February 2018, Pages 226-231
Journal: Microelectronics Reliability - Volume 81, February 2018, Pages 226-231
نویسندگان
Subhadeep Mukhopadhyay, Yung-Huei Lee, Jen-Hao Lee,