کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
495994 862846 2012 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Optimization of single variable functions using complete hardware evolution
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر نرم افزارهای علوم کامپیوتر
پیش نمایش صفحه اول مقاله
Optimization of single variable functions using complete hardware evolution
چکیده انگلیسی

A genetic algorithm (GA) is a computer based search optimization technique that uses the Darwinian “Theory of Evolution” as a model for finding exact and approximate solutions. GAs belong to a large family of heuristic algorithms called evolutionary algorithms (EA) which are being increasingly utilized for solving complex optimization and search problems. The large computation time consumed by a GA implemented in software makes it unsuitable for real time applications. This hurdle is overcome by shifting the implementation to hardware, which drastically speeds up the time factor, thus presenting a scope for real time applications. This paper presents a complete hardware evolution (CHE) that is implemented on a single Field Programmable Gate Array (FPGA). An important advantage here is that, the knowledge of the proprietary configuration bit – stream's structure is not required. The hardware is used here for evaluating certain fitness functions and to evolve optimal solutions for single variable functions. A distinct feature of this CHE implementation is that an off-the-shelf FPGA is used without any other additional soft/hard ware support. The design uses five modules along with one memory module, totally constructed on the Configurable Logic Block (CLB) logic of the FPGA. The coding is done using VHDL and simulated using Xilinx ISE 9.1i. The Joint Test Action Group (JTAG) protocol is used to download the configuration bit stream to the FPGA. This hardware GA engine is evaluated with different chromosome lengths/selection methods/crossover methods. Compared with the previous implementations, an enhancement in speed, number of generations required for obtaining the optimal solution and area utilization is observed. The results have shown a shift from seconds to few nanoseconds when moving from software simulation to hardware implementation. Resource utilization for the different functions implemented varies from 0% to 94% approximately. A decrease of about 77.3% in the number of generations required to reach the global maxima is also witnessed.

This paper presents a Complete Hardware Evolution (CHE) that is implemented on a single Field Programmable Gate Array (FPGA). An important advantage here is that, the knowledge of the proprietary configuration bit – stream's structure is not required. The hardware is used here for evaluating certain fitness functions and to evolve optimal solutions for single variable functions. A distinct feature of this CHE implementation is that an off- the- shelf FPGA is used without any other additional soft/hard ware support. The design uses five modules along with one memory module, totally constructed on the Configurable Logic Block (CLB) of the FPGA.Figure optionsDownload as PowerPoint slideHighlights
► First CHE for optimisation.
► Implementation of the complete algorithm including the required memory on the CLB logic of a single FPGA.
► Inclusion of user defined parameters to suit varying requirements.
► Support for different types of functions.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Applied Soft Computing - Volume 12, Issue 4, April 2012, Pages 1322–1329
نویسندگان
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