A Perspective on Collaboration with Interconnects & Routing in Network on Chip Architectures

As VLSI technology advances, the number of modules on a chip multiplies and thus the solutions for on-chip communication are evolving to support the new paradigm in inter-module communication on System on Chip (SOC). Those System on Chip, Current chip designs incorporate more complex multilayered and stack segmented interconnection buses with various routing architectures results in a Network on Chip. These, traditional solutions, which were based on a combination of shared-buses and dedicated module-to-module wires, scalability limit, and are no longer adequate for System on Chip/Network on Chip. On-chip architectures have been optimized for a non-chip environment before the multi-core challenge became the focus of processor chip architecture through the latency and the throughput. This evolution of on-chip interconnects may evoke feelings of among networking old-timers. The considerations that have driven data communication from shared buses to packet-switching networks and to routing protocols such as spatial reuse, multi-hop routing, flow and congestion control etc., will inevitably drive the challenges raised in the design of network interfaces with the segmented stack layered mechanism, and potentially managing the critical resources designed for on-chip modules.