Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High-dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time-independent process-induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in BTI degradation. Since time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time-zero variability on all of these effects simultaneously. Accordingly, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~ 1000 nm2) in 30 nm technology, we observe significant effects of Random Dopant Fluctuation (RDF) on BTI-induced variability (σΔVth). In addition, circuit analysis reveals similar trend in performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered in variation-tolerant circuit design.