Investigation of read disturb in split-gate memory and its feasible solution

- The read disturb in split-gate memory is investigated.
- The influences from temperature, process variation and endurance are checked.
- The suppression of read disturb by tunnel oxide traps is observed.
- Feasible solutions to reduce read disturb during chip testing is proposed.

The intrinsic read disturb mechanism in split-gate memory cells has been studied based on large amounts of experimental data and simulation results of 0.11 μm NOR SuperFlash® technology memory cells. It is shown that non-planar Floating Gate (FG) structure induced field enhance effect helps to cause Fowler-Nordheim Tunneling (F-N tunneling) in tunnel oxide during read operation, which will further lead to the leakage of electrons from FG to Word Line (WL). Then, the sensitivity of read disturb to process variation is investigated to expound the difference between typical cells and weak cells. The experiment has also demonstrated the weakening of read disturb due to induced tunnel oxide traps after program/erase (P/E) cycles. Based on these findings, we have rationally proposed possible solutions to reduce the read disturb on the perspectives of chip testing. The study of intrinsic read disturb mechanism is significant to the scaling of split-gate memory technology as well as to the assessment of read disturb risk in split-gate memory products.