Improving FPGA repair under real-time constraints

• An approach to repair FPGA-systems under real time constraints is proposed.
• The approach dynamically chooses an optimized configuration frame to start scrubbing.
• A translation circuit converts diagnosis signatures into the chosen frame.
• A compression heuristic provides translation circuits with manageable sizes.
• Improvements in probability of successful repair and failures in time are measured.

Field Programmable Gate Arrays (FPGAs) are very useful devices for the development of real-time systems, due to their flexibility, performance and reduced design costs. Special care should be taken, however, when considering the occurrence of faults, which is a pressing concern for space applications and critical systems in general, and also growingly relevant for any application using aggressively scaled manufacturing technologies. In the particular case of FPGAs, errors in the configuration memory pose a major dependability threat, and their repair is typically performed by means of scrubbing. The attainable repair time of traditional scrubbing-based approaches, however, may be too long for real-time systems, causing deadlines to be missed. In this work we propose a partial reconfiguration approach that aims at repairing configuration errors under real-time constraints. It relies on fine-grained error detection and a repair mechanism that is finely tuned to maximize the probability of meeting a given deadline.