Low-power MicroVrms noise neural spike detector for implantable interface microsystem device

• An ultra-low-power and low-noise detector based on NEO is implemented using standard CMOS process.
• The NEO detector circuit CMOS-based is realised using sub-threshold technique.
• We study the noise of NEO circuit and obtain the MicroVrms noise result.
• We test the chip of NEO detector about the current consumption, noise, and detecting function.

In this paper, an ultra-low-power and low-noise spike detector is proposed for massive integration in the implantable multichannel brain neural recording device. The detector circuit with nonlinear energy operator (NEO) algorithms achieves the spike detecting from action potential including complex noise. The spike detector circuit consists of a differentiator with a fully-differential structure and a multiplier based on CMOS translinear using sub-threshold technique. The differentiator has the steepness of a transmission function with frequency +20 dB/dec, frequency response from 10 Hz to 10.5 kHz. The linear range of multiplier is from −0.9 V to 0.9 V at VDD = ±1.65 V. The spike detector is implemented in 0.35 μm technology with fully-CMOS process. One detector die size is 0.0187 mm2 and its total current consumption of 825 nA. As is demonstrated by measured results, the proposed circuit has detected the instantaneous energy of the input real spike signals well, which the noise of small than 218 μVrms over a nominal bandwidth of 500–10.5 kHz.