An improved multilevel cell programming technique for 4-bits/cell localized trapping SONOS memory devices

As the cell size scales down to 90 nm node, the mismatch of spatial charge distribution dramatically aggravates the reliability degradation of localized trapping polysilicon–oxide–nitride–oxide–silicon (SONOS) memory, especially in multilevel cell and multi-bits/cell applications. The secondary electron injection (SEI) is thought to be the root cause of mismatch between injected electrons and holes. A channel hot electron injection (CHEI) programming technique with a positive substrate bias was proposed to effectively suppress SEI effect. In this work, a similar programming method is used in 90 nm localized trapping SONOS devices for multilevel cell and multi-bits/cell storage. In contrast to the reported positive substrate biased CHEI programming, we apply a source bias of 1 V instead of 0 V to prevent the forward-biased source/substrate junction so that the programming power consumption is greatly reduced. It is experimentally found that a sharp electron profile near the junction edge is obtained. A better matched profile of the injected electrons and holes substantially improves the cycling endurance and data retention of 4-bits/cell memory at the four-level states.