3D finite element modeling of 3D C2W (chip to wafer) drop test reliability: Optimization of internal architecture and materials

• We use the FEM calculation to optimize the design of a 3D microelectronic component.
• The drop test is used to estimate the mechanical reliability.
• The mechanical reliability is sensitive to the TSV location.
• The estimated failure area is sensitive to the molding resin’s mechanical properties.
• We study the effect of solder reflow residual stress on the 3D C2W reliability.

3D-WLSiP appears as a way to keep increasing density of microelectronic components. The C2W 3D integration use wafer-level processes to improve throughput. This technology gives a high yield and a good flexibility for the choice of internal architectures and assembling techniques. The reliability of 3D components has to be evaluated on mechanical demonstrator with daisy chain before real production. Modeling has proven to be a very efficient tool for design optimization. In this paper, 3D FEM modeling and submodeling techniques are employed to compare the dynamic response of several 3D C2W components under drop test loading conditions. The impacts of possible errors in thin layers elastic modulus estimation are studied. The behavior of the Face To Face (F2F) and the Back To Face (B2F) design for 3D integration are compared. The effects of TSVs repartition in silicon die and molding resin’s mechanical properties are discussed. The reliability evaluation criterion is chosen as maximum shear plastic strain of critical bump. The results have been used in choosing of the optimal design and materials properties for real production.