Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

• To investigate the MIM and MOM capacitors in a 65 nm CMOS process.
• MOM capacitor can be directly realized by the metal interconnections.
• MOM capacitor is with higher capacitance density and lower fabrication cost.
• The impact of gate leakage current on ESD protection circuit was presented.
• Gate leakage issue in ESD protection circuit can be overcome by MOM capacitor.

Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828 μA to 358 nA at 25 °C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process.