Secondary ESD clamp circuit for CDM protection of over 6 Gbit/s SerDes application in 40 nm CMOS

Novel secondary ESD clamp solutions to boost CDM robustness for both RX (input) and TX (output) circuits along with dual diode of primary ESD clamp to meet over 6-Gbit/s SerDes are presented. For RX circuit, active PMOS clamp with no voltage overshoot is used as secondary clamp to GND. For TX circuit, by constructing a secondary ESD path through the pre-driver and pumping-up the gate node of the main-driver using output impedance of pre-driver, an additional series resistor deteriorating SerDes performance is not needed for secondary clamp.