Analysis of fluid/structure interaction: Influence of silicon chip thickness in moulded packaging

Experimental and simulation studies of the three-dimensional (3D) analysis of fluid/structure interaction (FSI) in moulded packaging are presented in the current paper. The miniature size of integrated circuit package and the high cost of experimental setup make FSI visualization in actual packaging difficult. In the present study, a scaled-up moulded package was fabricated to observe the FSI phenomenon in package encapsulation by experiments. Virtual modelling using the Mesh-based parallel Code Coupling Interface method was employed to describe the physics of FSI and validate the experimental results. The FSI analysis was extended to the effects of different silicon chip thicknesses (50, 100, 150, 200, and 250 μm) on actual-size packaging. The silicon chip and solder bump structures were evaluated in relative to stress and deformation. The mechanisms of flow-front filling and air traps were also experimentally investigated. The FSI phenomenon of scaled-up packaging was observed. The predicted flow front and chip deformation were well validated by the experiments. Hence, the virtual modelling presented in the current study was proven excellent in handling packaging problems.

Experimental and FLUENT results in moulded packaging.Figure optionsDownload as PowerPoint slideHighlights
► We carry out the scaled-up experimental work of moulded IC packaging.
► We observe the mechanisms of flow-front and air traps in the experiment.
► The FSI analysis was used to predict the flow front and deformation during the encapsulation process.
► The maximum displacement and von Mises stress decrease exponentially with the increase of chip thickness.
► The downward chip deformation restricts the flow front and encourages the void formation beneath the chip.