High-κ related reliability issues in advanced non-volatile memories

In the last decade, important technology solutions have been proposed to scale down Flash memory devices beyond the 30 nm node. The most important innovations are the introduction of charge trapping layer and high-κ materials in both bottom and top dielectric stacks. Such innovations allow reducing both the bottom dielectric thickness and the Program/Erase (P/E) voltages, while maintaining the P/E performances without degrading (theoretically) the memory device reliability. Theoretical advantages and reliability issues of these important innovations will be reviewed by addressing physical mechanisms responsible of reliability degradation. In particular, the reliability consequences of the discrete charge storage and of the high-κ band-gap engineered barriers bottom and top dielectric stacks will be carefully analyzed, relating high-κ material properties to memory device performances and reliability.