SPICE modelling of hot-carrier degradation in Si1–xGex S/D and HfSiON based pMOS transistors

Hot-carrier degradation in pMOS transistors with Si1–xGex implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a better device performance, these devices are more sensitive to hot-carrier degradation at both the device and circuit levels.