Electromigration performance of Through Silicon Via (TSV) – A modeling approach

The electromigration (EM) performance of Through Silicon Via (TSV) in silicon interposer application are studied using Finite Element (FE) modeling. It is found that thermo-mechanical stress is the dominant contribution factor to EM performance in TSV instead of the current density. The predicted failure site is dependent on the process technology, and exhibits asymmetric behavior if different process is used between the top and bottom metallization of a TSV. Modeling is also done for two different coverage patterns of top metallization, namely (i) the metal line covers the via completely, and (ii) the metal line only extends to the centre of the via, covering half of the via. The simulation results of the latter model show the existence of a second EM failure site and worse EM performance is expected. This additional possible EM failure site is further confirmed through dynamic simulation of void growth.