Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown

Low-k time-dependent dielectric breakdown (TDDB) has been found to be a function of metal linewidth, when the distance between the lines is constant. Modeling requires determining the relationship between TDDB and layout geometries. To determine this relationship, comb test structures have been design and implemented in 45 nm technology. In this work, low-k dielectric breakdown, low-k dielectric vulnerable areas, and linewidth variation are linked to full chip lifetimes.