کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
545195 | 1450553 | 2010 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed in a 32 nm bulk CMOS technology. The devices which were developed from process and layout information were calibrated to experimental results in the low current DC and high-current/high-temperature ESD regime. The failure currents of ESD devices correlated to the experimental data to within 15% and the failure location of the devices in TCAD were confirmed using failure analysis.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 50, Issues 9–11, September–November 2010, Pages 1367–1372
Journal: Microelectronics Reliability - Volume 50, Issues 9–11, September–November 2010, Pages 1367–1372
نویسندگان
T. Cilento, M. Schenkel, C. Yun, R. Mishra, J. Li, K. Chatty, R. Gauthier,