Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. The paper presents a comparison between four ESD protections in CMOS 32 nm node. Dynamic and static triggering circuits are investigated and SCR and bi-SCR are compared. Each structure is characterized through TLP and protects up to 2 kV HBM stresses.