Investigation on BIST assisted failure analysis on digital integrated circuits

Built in self tests (BISTs) on integrated circuits are one approach of maintaining fault coverage and device’s testability without increasing the test time. As an additional benefit, for the purpose of failure analysis fault simulation down to node level can be achieved. However, regarding defect localization common FA techniques are still mandatory.In this paper, we present BIST assisted case studies on functional failing integrated circuits. Starting from a fault simulation, defect localization will be done by using conventional failure analysis techniques. After successfully determining the physical defect, we will compare its effect on the affected nodes to the initial fault simulation.