Characterising gate dielectrics in high mobility devices using novel nanoscale techniques

Strained Si and strained SiGe layers can increase the speed of MOS devices through enhanced electron and hole mobilities compared with bulk Si. However, epitaxial growth of strained Si and SiGe layers induces surface roughness which impacts gate dielectric properties including leakage, breakdown and interface traps. Gate dielectric quality is conventionally studied at a macroscopic level on individual transistors or capacitors. To understand precisely the effect of roughness on the quality and reliability of dielectrics on high mobility substrate devices requires high spatial resolution characterisation techniques. Device processing modifies the dielectric/semiconductor interface compared with its initial form. Therefore nanoscale analysis on completed devices is necessary. In this work, we present new techniques to enable gate leakage analysis on a nanoscale in fully processed high mobility MOSFETs. This is achieved by careful selective removal of the gate from the dielectric followed by C-AFM measurements on the dielectric surface. Raman spectroscopy, AFM and SEM (EDX) confirmed complete layer removal. The techniques are applied to strained Si devices which have different surface morphologies and different macroscopic electrical data. Dielectric reliability is also assessed through device stressing.