Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures

The effect of interface state trap density, DitDit, on the current–voltage characteristics of four recently proposed III–V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δδ-doping below the channel, a buried channel design with δδ-doping, and implant-free quantum-well HEMT-like structure with no δδ-doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δδ-doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.