Impact of bias condition on 1/f noise of dual-gate depletion type MOSFET in linear region and consequences for noise diagnostic application and modelling

This paper presents experimental and numerical results for 1/f noise of depletion-type dual-gate MOSFET (DGMOSFET) in the linear region of the output ID–VDS characteristics. In this region, both DGMOSFET inner transistors operate in either linear or non-linear region each. Gate-to-gate interelectrode spacing influence is taken into account in ID–VDS modelling with the effective parameter meff = μeff2Leff1/μeff1Leff2. For low bias conditions, the parameter meff can be reduced to the ratio of inner transistors channel effective lengths. A model for the normalized 1/f noise parameter and methodology for its calculation valid for the DGMOSFET linear region have been proposed. Due to interdependence of the inner transistors bias condition, their participation in total noise is controlled by weighting factors. This fact must be taken into account in the noise diagnostic procedure for DGMOSFET analysis.