Test generation at the algorithm-level for gate-level fault coverage

We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input–output pin pair and an input–input–output pin triplet fault models. The basic properties of these models are analyzed. Random test generation was implemented on the base of these fault models. ISCAS’85 and ITC’99 benchmark circuits were used for the experiments. The obtained results for the presented fault models were compared with the gate level test generation. The problem of termination of random search is explored and the solution is proposed.