Yield challenges in wafer stacking technology

Wafer stacking technology offers a higher performance in a smaller size with a lower cost option for microelectronic industries. However, it suffers from a compound yield loss which becomes a key challenge and a limiting factor in this technology. A compound yield loss in wafer stacking has been analyzed and yield challenges have been presented. Assuming a random defect density per wafer and no yield fallout from stacking processes, the compound yield of a bonded wafer pair has been estimated with the most commonly used yield model. As a result, it is proposed that a die area reduction for wafer stacking is needed in order to offer a great yield advantage. Both wafer testing and wafer size are also proven to influence significantly a die yield in a bonded wafer pair.