A strategy for damage assessment of thermally stressed copper vias in microelectronic printed circuit boards

The thermal fatigue of plated-through vias remains a subject of concern, particularly when exposed to the high operating temperatures associated with automotive applications. In this paper the performance of different types of copper vias in different positions of a printed circuit board is analyzed. To this end a two-scale finite element analysis under the loading conditions of thermal cycling is employed. A new material model for the electrolytically deposited copper accounts for large elastic and plastic deformations and, additionally, for the growth of pores within the material.It is common practice to extrapolate the plastic straining computed within few steps of thermal cycling by means of a Coffin–Manson-Equation. We critical examine this strategy and point out, that a certain number of about 20 cycling steps is necessary to obtain meaningful extrapolations. Furthermore, an extrapolation of the computed porosity up to critical values allows similar conclusions.The presented strategy can serve as a predictive tool for plated through holes and vias and can reduce the need of repetitive experimental failure tests.